The present invention relates to a data processing system capable of performing a saturation processing function on the occurrence of arithmetic overflow. This invention also relates to a register file adaptable to such a data processing system.
Recent significant developments in the field of LSI technology provide the means of manufacturing high-performance digital signal processors. Sophisticated data processing including various arithmetic operations (such as addition/subtraction and multiplication) can now be performed in a one chip digital signal processor. Such a high-performance digital signal processor has a particular application in the field of mobile telecommunication such as portable telephone apparatus. Mobile telecommunication requires compression and decompression of large volumes of information, and there have been strong demands for high-speed data processing to meet the requirements of portable telephone apparatus.
Various high-speed data processors capable of high-speed data processing have been known in the art. For example, a high-speed data processing system employing a pipeline control architecture is known. This data processing system incorporates therein a small storage-capacity, fast register file in addition to a large storage-capacity memory such as an SRAM (static random access memory) and a slow memory such as a R0M (read-only memory). The data processing system is formed by establishing bus connections between the register file made up of a plurality of data registers for storing data and a plurality of arithmetic units such as an arithmetic-logic unit and a multiplier unit. The register file is used to store arithmetic data. The arithmetic-logic unit receives two operands from the register file and adds together the received two operands in response to, for example, an addition instruction. Data representing the result of an addition operation in the arithmetic-logic unit is written into a selected data register of the register file. On the other hand, the multiplier unit receives two operands from the register file and multiplies together the received two operands in response to a multiplication instruction. Data representing the result of a multiplication operation in the multiplier unit is written into a selected data register of the register file.
An arithmetic operation of two fixed-point numbers X and Y represented in two's complement format is described here. The most significant bits (MSBs) of the numbers X and Y are sign bits. If the MSB of a number is 0, this indicates that the number is positive. On the other hand, if the MSB of a number is 1, this indicates that the number is negative. The radix point is located between the MSB and the second most significant bit. Accordingly, -1.ltoreq.X&lt;1 and -1.ltoreq.Y&lt;1. In other words, the largest in absolute value of all the positive numbers is represented as 011 . . . 1 in binary notation and the largest in absolute value of all the negative numbers is represented as 100 . . . 0 in binary notation. The latter binary number, i.e. 100 . . . 0, is equal to a number of -1 in decimal notation.
An occurrence of arithmetic overflow in an arithmetic operation (such as an addition/subtraction operation and a multiplication operation) sometimes results in the requirement that saturation processing be performed on the result of the arithmetic operation. For example, if addition of two positive numbers causes an arithmetic overflow therefore to produce a negative arithmetic result, such a negative sum result is then corrected to a positive saturation value (i.e. a number having the largest absolute value in all positive numbers, 011 . . . 1 in the foregoing example). If addition of two negative numbers produces a positive arithmetic result, such a positive sum result is then corrected to a negative saturation value (i.e. a number that has the largest absolute value in all negative numbers, 100 . . . 0 in the foregoing example). If subtraction of a negative number from a positive number produces a negative arithmetic result, such a negative remainder result is then corrected to a positive saturation value. On the other hand, if subtraction of a positive number from a negative number produces a positive arithmetic result, such a positive remainder result is then corrected to a negative saturation value. Further, if multiplication of two negative numbers causes an arithmetic overflow therefore to produce a negative result, such a negative product result is then corrected to a positive saturation value. The occurrence of arithmetic overflow is limited to a multiplication of -1 by -1, which can be rewritten to 100 . . . 0 by 100 . . . 0 in binary notation.
In commonly-used data processing systems, at the moment when an overflow occurs in an arithmetic operation, either a positive saturation value or a negative saturation value is immediately written into a data register as a substitute of the result of the arithmetic operation.
In a conventional data processing system, an overflow signal, indicative of the presence or absence of an occurrence of arithmetic overflow, is generated based on the result of an arithmetic operation. Thereafter, either a positive saturation value or a negative saturation value obtained by correction made on the arithmetic operation result is written into a data register. Such a procedure causes delays in completing the execution of the arithmetic operation.